1. Field of the Invention
The present invention generally relates to integrated circuit devices and, more particularly, to memory devices that involve sensing operations, su ch as dynamic random access memory (DRAM) devices.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for dynamic random access memory (DRAM) devices. A DRAM device is generally a volatile memory device where each memory cell consists of one transistor and one capacitor. Such memory cells require periodic refreshing to protect the data stored in a memory cell from corruption or decaying over time. Refreshing is performed periodically (e.g., about every 64 msec), as well as when an information content of the memory cell is accessed, for example, during a read or write operation. Common to such routines is a sensing operation, during which a content of the memory cell is asserted and refreshed.
Therefore, the sensing operation is one of most power-consuming operations performed in the DRAM devices. In battery-powered computer systems (e.g., palm-top computers, hand-held electronic devices, and the like), minimization of power consumption is critically important. In advanced DRAM devices, during the sensing operation, about a half of the power that is used to refresh an array of the memory cells may partially be recycled for sensing memory cells in the other array. However, there are limitations to such recycling schemes, as described below in reference to FIGS. 1-3.
FIG. 1A depicts a block diagram of an exemplary DRAM device 100. The DRAM device 100 generally comprises control circuitry 102 and a memory circuitry 104. The control circuitry 102 generally includes a logic circuit 105 including various control circuitry such as command and address decoders, self refresh circuitry, and the like, as well as a sensing circuit 106. The sensing circuit 106 includes circuitry utilized to generate voltage signals used to access (e.g., sense) data stored in various memory cell arrays 138.
Each memory cell array 138 may have a corresponding array of bit line sense amplifiers (BLSAS) 140, collectively forming a memory block 136. In devices implementing BLSA power line charge recycling, BLSA arrays are divided into an “upper” group of BLSA arrays 140U and a “lower” group of BLSA arrays 140L. As used herein, the term recycling generally refers to the utilization of charges supplied by the external power source 110 to the upper group 140U in sensing operations involving the lower group 140L. The power lines of the upper and lower groups are supplied with the voltage signals generated by the sensing circuit 106, via a BLSA power bus 116.
As illustrated in FIG. 1B, the upper and lower BLSA groups 140 each utilize two power lines (208 and 210) for sensing bit line pairs 202 of memory cells 200 of a corresponding array 138 (VH_BLSA1/VL_BLSA1 and VH_BLSA2N/L_BLSA2, respectively). Recycling typically occurs by transferring charge from the lower voltage line of the upper group (VL_BLSA1) to the higher voltage line of the lower group (VH_BLSA2). The concepts of charge recycling may be best described with reference to FIG. 2, which illustrates a conventional sensing circuit 1062.
As illustrated in FIG. 2, a bit line sensing controller 1342 may generate a set of signals ΦPRE-CHARGE and ΦACTIVE to control the application of voltage signals applied to power lines of the upper and lower group BLSA arrays 140, via a switch array 1322. The upper group 140U utilizes an upper reference voltage VINT and an intermediate voltage VINT—M to power the sensing operations, while the lower group 140U utilizes VINT—M and a lower reference voltage (e.g., GND in FIG. 2) to power the sensing operations. The voltage signals VINT, VINT—M (approx VINT/2) and GND are generated by a voltage regulator 1302. FIG. 3 illustrates an exemplary timing diagram of the ΦPRE—CHARGE and ΦACTIVE signals for sensing operations performed by sensing circuit 1062.
As illustrated in FIG. 3, at a time T1, prior to sensing, the power lines of each group of BLSA arrays 140 have been precharged (e.g., by equalizing each corresponding pair of power lines via switches 222PC while the bit line sensing controller 1342 drives ΦPRE—CHARGE high). As illustrated, VH_BLSA1 and VL_BLSA1 are precharged to a first level VPCG1, while VH_BLSA2 and VL_BLSA2 have been precharged to VPCG2. Sensing operations begin at a time T2, when the sensing controller 1342 asserts ΦACTIVE, causing switches 222U and 222L to close, coupling VH_BLSA1 to VINT and VL_BLSA2 to GND. As a result, VH_BLSA1 increases to VINT, while VL_BLSA2 decreases to GND.
At the beginning of the sensing operations, the power lines VL BLSA1 and VH_BLSA2 are also coupled together, causing charge to be transferred from VL_BLSA1 to VH_BLSA2, as VL_BLSA1 decreases from VPCG1 to VINT_M causing a corresponding increase in VH_BLSA2 from VPCG2 to VINT M (this increase is denoted in FIG. 3 as VREC). Thus, current consumption from the external power source 110 is reduced, as charge used to precharge the upper group 140U is utilized in the sensing operations involving the lower group. At a time T3, the bit line sensing controller 1342 de-asserts ΦACTIVE, signaling an end of the sensing operations, and decoupling the power lines from the internal power supply 1302. At a time T4, the power lines are again precharged, in preparation of the next sensing operation, by equalizing the power lines via switches 222PC.
Thus, during the sensing operation, the conventional sensing circuit 1062 may recycle approximately 50% of the power (or charge) used in the upper group for sensing by the lower group. To provide such recycling of the charge, the level of VINT—M should be less than half the output voltage VEXT of the external power source 110. Additionally, of course, the voltage differential between the power lines of the BLSA arrays 140 must be sufficient to maintain full voltage logic levels on the sensed bit lines (which is based on switching transistor threshold voltages for particular device technologies). As external voltage levels continue to shrink, satisfying these requirements of VINT—M may become more difficult.
Therefore, there is a need in the art for an improved sensing circuit configuration for use in memory devices, such as dynamic random access memory (DRAM) devices.